MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 325

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 9
DDR Memory Controller
9.1
The fully programmable DDR SDRAM controller supports most JEDEC standard x8, x16, or x32 DDR2
and DDR memories available. In addition, unbuffered and registered DIMMs are supported. However,
mixing different memory types or unbuffered and registered DIMMs in the same system is not supported.
Built-in error checking and correction (ECC) ensures very low bit-error rates for reliable high-frequency
operation. Dynamic power management and auto-precharge modes simplify memory system design. A
large set of special features, including ECC error injection, support rapid system debug.
Figure 9-1
Section 9.5, “Functional Description,”
Freescale Semiconductor
Introduction
is a high-level block diagram of the DDR memory controller with its associated interfaces.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
In this chapter, the word ‘bank’ refers to a physical bank specified by a chip
select; ‘logical bank’ refers to one of the four or eight sub-banks in each
SDRAM chip. A sub-bank is specified by the 2 or 3 bits on the bank address
(MBA) pins during a memory access.
contains detailed figures of the controller.
NOTE
9-1