MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 209
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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- Download datasheet (12Mb)
This two-level structure is shown in
Level-1 MMUs have the following features:
The level-2 MMU has the following features:
Freescale Semiconductor
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•
•
•
•
•
•
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Four-entry, fully associative TLB array that supports all nine page sizes
64-entry, 4-way set-associative TLB 4-Kbyte array that supports 4-Kbyte pages only
Hardware partially managed by L2 MMU
Supports snooping of TLBs by both internal and external tlbivax instructions
A 16-entry, fully associative L2 TLB array (TLB1) that supports all nine variable page sizes
TLB array (TLB0) that supports only 4-Kbyte pages, as follows:
— e500v1—256-entry, 2-way set-associative TLB array
— e500v2—512-entry, 4-way set-associative TLB array
Hardware assist for TLB miss exceptions
Software managed by tlbre, tlbwe, tlbsx, tlbsync, tlbivax, and mtspr instructions
Supports snooping of TLB by both internal and external tlbivax instructions
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
To instruction unit
To load/store unit
Registers
MAS
Figure
D-L1VSP
TLB Array
I-L1VSP
4-Entry
16-Entry
4-Entry
(TLB1)
L1 Instruction MMU
32-Kbyte D-Cache
32-Kbyte I-Cache
Figure 5-8. MMU Structure
Memory Unit
L1 Data MMU
L2 MMUs
Unified
5-8.
Tags
Tags
256/512-Entry
D-L1TLB4K
I-L1TLB4K
64-Entry
64-Entry
TLB Array
(TLB0)
Core Interface
Data Line
FIll Buffer
Instruction Line
FIll Buffer
Core Complex Overview
5-23
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