MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 492

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Security Engine (SEC) 2.1
12-12
0x3_11C0–0x3_11DF Gather link tables
0x3_12C0–0x3_12DF Gather link tables
0x3_13C0–0x3_13DF Gather link tables
0x3_1180–0x3_11BF DB1—Crypto-channel 1 descriptor buffers
0x3_11E0–0x3_11FF Scatter link tables
0x3_1280–0x3_12BF DB2—Crypto-channel 2 descriptor buffers
0x3_12E0–0x3_12FF Scatter link tables
0x3_1380–0x3_13BF DB3—Crypto-channel 3 descriptor buffers
0x3_13E0–0x3_13FF Scatter link tables
Address Offset
(AD 17–0)
0x3_1148
0x3_1208
0x3_1210
0x3_1240
0x3_1248
0x3_1308
0x3_1310
0x3_1340
0x3_1348
0x3_1408
0x3_1410
0x3_1440
0x3_1448
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
FF1—Crypto-channel 1 fetch FIFO
address register
[0–7]
CCCR2—Crypto-channel 2 configuration
register
CCPSR2—Crypto-channel 2 pointer
status register
CDPR2—Crypto-channel 2 current
descriptor pointer register
FF2—Crypto-channel 2 fetch FIFO
address register
[0–7]
CCCR3—Crypto-channel3 configuration
register
CCPSR3—Crypto-channel3 pointer status
register
CDPR3—Crypto-channel 3 current
descriptor pointer register
FF3—Crypto-channel 3 fetch FIFO
address register
[0–7]
CCCR4—Crypto-channel 4 configuration
register
CCPSR4—Crypto-channel 4 pointer
status register
CDPR4—Crypto-channel 4 current
descriptor pointer register
FF4—Crypto-channel 4 fetch FIFO
address register
Table 12-3. SEC Address Map (continued)
Register
Channel 2
Channel 3
Channel 4
Access
R/W
R/W
R/W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0007
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0007
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0007
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
Reset
Freescale Semiconductor
12.5.1.4/12-101
12.5.1.5/12-102
12.5.1.6/12-102
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12.5.1.1/12-92
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Reference