MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 898

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
followed by a default rule; thus, if no VLAN tag appears in the received frame, the TOS rules are checked,
or the default is activated should no IP header be present.
The rule cluster feature is used to conditionalize evaluation of rule sets. Typically, this avoids evaluating
rules based on properties that may not be valid or relevant to the filing or filtering decision. For example,
TCP-related rules might be clustered behind a guard rule that checks that a TCP header has appeared and
the IP address matches our home address. Property 1—the parse flags property—is provided specifically
to check the characteristics of the received frame and the parser error status. The mask_register is typically
assigned beforehand to extract specific flags, in which case care should be taken that mask_register be
reassigned an appropriate mask vector for following comparisons.
In many cases it will be possible to write the entire filer table before using eTSEC, as the rule set is static.
However, dynamic rule updates can be supported by pre-allocating partially instantiated rule sets, which
software rewrites as necessary. Rules that are not instantiated should be composed of empty entries, as
indicated in
eTSEC’s receive function.
15.6.5.1.6
This example, shown in
This matches against property 1001, comparing each specific priority level in order to associate them with
a RxBD ring index. Note that if a VLAN tag does not appear in the frame, the parser passes priority 0 to
the filer, which will always match the rule at entry 7 and terminate the table search.
15.6.5.1.7
This example demonstrates use of rule priority for determining class selector codepoints (RFC 2474) from
the IP TOS property. An example filer table is shown in
the first rule matched terminates the search, hence successively lower Diff-Serv codepoint ranges can be
compared in each step until the default (zero or greater) range is reached. By default, property 1010 (IP
15-166
Table
Entry
0
1
2
3
4
5
6
7
CLE REJ AND
0
0
0
0
0
0
0
0
Table
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Filer Example—802.1p Priority Filing
Filer Example—IP Diff-Serv Code Points Filing
0
0
0
0
0
0
0
0
15-141. In many cases empty entries can be overwritten by software without stopping
RQCTRL Fields
0
0
0
0
0
0
0
0
Table
Table 15-143. Filer Table Example—802.1p Priority Filing
000_000
000_001
000_010
000_011
000_100
000_101
000_110
000_111
Q
15-143, illustrates how to file frames according to layer 2 802.1p priority.
CMP
00
00
00
00
00
00
00
00
1001
1001
1001
1001
1001
1001
1001
1001
PID
0x0000_0007 File priority 7 to ring 0
0x0000_0006 File priority 6 to ring 1
0x0000_0005 File priority 5 to ring 2
0x0000_0004 File priority 4 to ring 3
0x0000_0003 File priority 3 to ring 4
0x0000_0002 File priority 2 to ring 5
0x0000_0001 File priority 1 to ring 6
0x0000_0000 File undefined 802.1p or priority 0 to
RQPROP
Table
ring 7—Default always matches
15-144. The example relies on the fact that
Comment
Freescale Semiconductor
0x0000_0C09
0x0000_1C09
0x0000_0009
0x0000_0409
0x0000_0809
0x0000_1009
0x0000_1409
0x0000_1809
RQCTRL
Word