UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 153

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(2) Capture/compare control register 0n (CRC0n: n = 0, 1)
Address: FF62H
Symbol
CRC00
Note
Cautions 1. The timer operation must be stopped before setting CRC00.
This register controls the operation of the 16-bit timer capture/compare registers (CR00n, CR01n).
CRC0n is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CRC0n to 00H.
If both the rising and falling edges have been selected as the valid edges of the TI000 pin, capture is not
performed.
2. When the clear & start mode entered on a match between TM00 and CR000 is selected by
3. To ensure the reliability of the capture operation, the capture trigger requires a pulse longer
CRC020
CRC010
CRC000
16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a capture
register.
than two cycles of the count clock selected by prescaler mode register 00 (PRM00) (refer
to Figure 8-22).
Figure 8-8. Format of Capture/Compare Control Register 00 (CRC00)
7
0
0
1
0
1
0
1
After reset: 00H
Operate as compare register
Operate as capture register
Capture on valid edge of TI010 pin
Capture on valid edge of TI000 pin by reverse phase
Operate as compare register
Operate as capture register
CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01
6
0
R/W
5
0
User’s Manual U14260EJ4V0UD
CR010 operating mode selection
CR000 operating mode selection
CR000 capture trigger selection
4
0
3
0
CRC020
Note
2
CRC010
1
CRC000
0
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