UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 344

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

342
Note Set SPT0 only in master mode. However, SPT0 must be set and a stop condition generated before the
Caution
Remark Bit 0 (SPT0) becomes 0 when it is read after data setting.
Cautions concerning set timing
• For master reception:
• For master transmission:
• Cannot be set at the same time as STT0.
• SPT0 can be set only when in master mode.
• When WTIM0 has been set to 0, if SPT0 is set during the wait period that follows output of eight clocks, note
• Once the SPT0 bit has been set, it is prohibited to set it again without clearing it.
Condition for clearing (SPT0 = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• When RESET is input
first stop condition is detected following the switch to the operation enabled status. For details, see 18.5.14
Other cautions.
SPT0
that a stop condition will be generated during the high level period of the ninth clock. WTIM0 should be
changed from 0 to 1 during the wait period following output of eight clocks, and SPT0 should be set during the
wait period that follows output of the ninth clock.
0
1
When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set during the ninth clock
and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to high impedance.
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to
high level. Next, after the rated amount of time has elapsed, the SDA0 line changes from low level
to high level and a stop condition is generated.
Figure 18-5. Format of IIC Control Register 0 (IICC0) (4/4)
Cannot be set during transfer.
Can be set only in the waiting period when ACKE0 has been set to 0 and slave has
been notified of final reception.
A stop condition cannot be generated normally during the acknowledgment period.
Therefore, set it during the waiting period after the ninth clock has been output.
User’s Manual U14260EJ4V0UD
Note
Stop condition trigger
Condition for setting (SPT0 = 1)
• Set by instruction