UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 243

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

13.6 Cautions for A/D Converter
(1) Power consumption in standby mode
(2) Input range of ANI0 to ANI7
(3) Conflicting operations
(4) ANI0/P10 to ANI7/P17
(5) Input impedance of ANI0 to ANI7 pins
(6) AV
<1> Conflict between A/D conversion result register 0 (ADCR0) write and ADCR0 read by instruction upon the
<2> Conflict between ADCR0 write and external trigger signal input upon the end of conversion
<3> Conflict between ADCR0 write and A/D converter mode register 0 (ADM0) write or analog input channel
<1> The analog input pins (ANI0 to ANI7) also function as input port pins (P10 to P17).
<2> If digital pulses are applied to the pin adjacent to a pin in the process of A/D conversion, the expected
The A/D converter stops operating in the standby mode. At this time, power consumption can be reduced by
setting bit 7 (ADCS0) and bit 0 (ADCE0) of A/D converter mode register 0 (ADM0) to 0 (see Figure 13-2).
The input voltages of ANI0 to ANI7 should be within the rated range. In particular, if a voltage of AV
or AV
will be undefined and the conversion values of other channels may also be affected.
This A/D converter executes sampling by charging the internal sampling capacitor for approximately 1/8 of the
conversion time.
Therefore, only the leakage current flows during other than sampling, and the current for charging the capacitor
flows during sampling. The input impedance therefore varies and has no meaning.
To achieve sufficient sampling, it is recommended that the output impedance of the analog input source be 10
k
A series resistor string of several tens of k
Therefore, when the output impedance of the reference voltage is too high, it seems as if the AV
series resistor string are connected in series. This may cause a greater reference voltage error.
REF
or less, or attach a capacitor of around 100 pF to the ANI0 to ANI7 pins (see Figure 13-22).
SS
end of conversion
ADCR0 read is given priority. After the read operation, the new conversion result is written to ADCR0.
The external trigger signal is not acknowledged during A/D conversion. Therefore, the external trigger
signal is not acknowledged during ADCR0 write.
specification register 0 (ADS0) write
ADM0 or ADS0 write is given priority. ADCR0 write is not performed, nor is the conversion end interrupt
request signal (INTAD0) generated.
When A/D conversion is performed with any of pins ANI0 to ANI7 selected, do not access port 1 while
conversion is in progress, as this may reduce the conversion resolution.
A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to
the pin adjacent to a pin undergoing A/D conversion.
pin input impedance
or lower is input (even if within the absolute maximum rating range), the conversion value of that channel
CHAPTER 13 A/D CONVERTER
User’s Manual U14260EJ4V0UD
is connected between the AV
REF
pin and the AV
SS
REF
pin.
REF
pin and the
or higher
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