UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 357

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

18.5.7 Interrupt request (INTIIC0) generation timing and wait control
and the corresponding wait control, as shown in Table 18-2.
(1) During address transmission/reception
(2) During data reception
(3) During data transmission
(4) Wait cancellation method
WTIM0
The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated
Notes 1. The slave device’s INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when
Remark The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and
0
1
• Slave device operation:
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
• By setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1
• By writing to IIC shift register 0 (IIC0)
• By setting a start condition (setting bit 1 (STT0) of IICC0 to 1)
• By setting a stop condition (setting bit 0 (SPT0) of IICC0 to 1)
Note Master only.
The four wait cancellation methods are as follows.
When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of ACK generation must be
determined prior to wait cancellation.
2. If the received address does not match the contents of slave address register 0 (SVA0) and extension
9
9
wait control are both synchronized with the falling edge of these clock signals.
Address
there is a match with the address set to slave address register 0 (SVA0).
At this point, ACK is generated regardless of the value set to IICC0’s bit 2 (ACKE0). For a slave device
that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIIC0 is generated at the falling edge of the
9th clock, but wait does not occur.
code is not received, neither INTIIC0 nor a wait occurs.
Notes 1, 2
Notes 1, 2
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
During Slave Device Operation
Table 18-2. INTIIC0 Generation Timing and Wait Control
Data Reception
8
9
Note 2
Note 2
Interrupt and wait timing are determined depending on the conditions described in
Notes 1 and 2 above, regardless of the WTIM0 bit.
the WTIM0 bit.
User’s Manual U14260EJ4V0UD
Data Transmission
8
9
Note 2
Note 2
Address
9
9
Note
Note
During Master Device Operation
Data Reception
8
9
Data Transmission
8
9
355