UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 279

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(5) Clock select register 2 (CKSEL2)
Address: FF92H After reset: 00H
This 8-bit register is used to select the input clock for the baud rate of UART2 and the transmit pulse width of
IrDA.
CKSEL2 is set by an 8-bit memory manipulation instruction.
RESET input clears CKSEL2 to 00H.
Note To rewrite TPS20 to TPS22, clear bit 7 (POWER2) of asynchronous serial interface mode register 2
Symbol
CKSEL2
(ASIM2) to 0.
TPW23
TPS22
7
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Figure 15-7. Format of Clock Select Register 2 (CKSEL2)
TPS22
TPW22
TPS21
Other than above
6
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Note
CHAPTER 15 SERIAL INTERFACE UART2
R/W
TPS21
TPW21
TPS20
5
0
1
0
1
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
User’s Manual U14260EJ4V0UD
Note
TPS20
External clock input to ASCK2
f
f
f
f
f
f
f
X
X
X
X
X
X
X
TPW20
/2
/2
/2
/2
/2
/2
/2
2
3
4
5
6
7
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Note
Selection of IrDA transmit pulse width of 1-bit data
Width of two f
Width of three f
Width of four f
Width of five f
Width of six f
Width of seven f
Width of eight f
Width of nine f
Width of ten f
Width of 11 f
Width of 12 f
Width of 13 f
Width of 14 f
Width of 15 f
Width of 16 f
Setting prohibited
Source clock of 8-bit counter
TPW23
3
SCK2
SCK2
SCK2
SCK2
SCK2
SCK2
SCK2
SCK2
SCK2
SCK2
TPW22
SCK2
SCK2
SCK2
SCK2
SCK2
2
clocks
clocks
clocks
clocks
clocks
clocks
clocks
clocks
clocks
clocks
clocks
clocks
clocks
clocks
clocks
TPW21
1
TPW20
0
n
0
1
2
3
4
5
6
7
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