UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 549

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Note fbr: Specified baud rate
Notes 1. On a start condition, the first clock pulse is generated after the hold period.
Transfer rate
Bit rate tolerance
Output pulse width
Input pulse width
SCL0 clock frequency
Bus free time
(between stop and start condition)
Hold time
SCL0 clock low-level width
SCL0 clock high-level width
Start/restart condition setup time
Data hold time
Data setup time
SDA0 and SCL0 signal rise time
SDA0 and SCL0 signal fall time
Stop condition setup time
Capacitive load per each bus line
Spike pulse width controlled by input filter
(j)
(k) I
Parameter
2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide an
3. If the device does not extend the SCL0 signal low hold time (t
4. The high-speed mode I
5. Cb: Total capacitance per bus line (unit: pF)
UART2 (infrared data transfer mode)
2
Note 1
C bus mode ( PD780076Y, 780078Y, 78F0078Y only)
SDA0 signal (with V
needs to be fulfilled.
described below must be satisfied.
• If the device does not extend the SCL0 signal low state hold time
• If the device extends the SCL0 signal low state hold time
t
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (t
= 1000 + 250 = 1250 ns by standard mode I
SU:DAT
Parameter
CBUS compatible master
I
2
CHAPTER 27 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS)
C bus
250 ns
Symbol
IHmin.
2
C bus is available in a standard mode I
of the SCL0 signal) with at least 300 ns of hold time.
4.0 V
4.0 V
4.0 V
4.0 V
f
t
t
t
t
t
t
t
t
t
t
Cb
t
Symbol
SCL
BUF
HD:STA
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
F
SU:STO
SP
V
V
V
V
User’s Manual U14260EJ4V0UD
DD
DD
DD
DD
Conditions
5.5 V
5.5 V
5.5 V
5.5 V
0
MIN.
250
Note 2
4.7
4.0
4.7
4.0
4.7
5.0
4.0
—
—
—
—
0
Standard Mode
2
C bus specification).
MAX.
1000
LOW
100
300
400
MIN.
—
—
—
—
—
—
—
—
—
—
4/f
1.2
2
), only the maximum data hold time t
C bus system. At this time, the conditions
X
20 + 0.1Cb
20 + 0.1Cb
100
TYP.
0
MIN.
Note 2
1.3
0.6
1.3
0.6
0.6
0.6
High-Speed Mode
—
—
0
0
Note 4
Note 5
Note 5
0.24/fbr
262062
MAX.
0.87
0.9
MAX.
400
300
300
400
Note
50
—
—
—
—
—
—
—
—
Note 3
Rmax.
+ t
Unit
bps
%
s
s
HD:DAT
Unit
SU:DAT
kHz
pF
ns
ns
ns
ns
547
s
s
s
s
s
s
s
s