UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 391

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

18.6 Timing Charts
slave devices as its communication partner.
which specifies the data transfer direction, and then starts serial communication with the slave device.
transmit data is transferred to the SO0 latch and is output (MSB first) via the SDA0 pin.
When using the I
After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)),
Figures 18-23 and 18-24 show timing charts of the data communication.
IIC shift register 0 (IIC0)’s shift operation is synchronized with the falling edge of the serial clock (SCL0). The
Data input via the SDA0 pin is captured into IIC0 at the rising edge of SCL0.
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
2
C bus mode, the master device outputs an address via the serial bus to select one of several
User’s Manual U14260EJ4V0UD
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