UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 267

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UPD78F0078GK-9ET-A

Manufacturer Part Number
UPD78F0078GK-9ET-A
Description
Manufacturer
Renesas Electronics America
Datasheet

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(3) Relationship between main system clock and baud rate
(4) Bit rate and pulse width
Baud rate
115.2
Bit Rate
Caution
Table 14-6 shows the relationship between the main system clock and the baud rate.
Table 14-7 lists the bit rate, bit rate error tolerance, and pulse width values.
(kbps)
Notes 1. Operation with f
Remark f
Figure 14-13. Data Format Comparison Between Infrared Data Transfer Mode and UART Mode
Note 1
2. When a digital noise eliminator is used in a microcontroller operating at 1.41 MHz or above.
Start bit
Start bit
Bit time
Bit Rate Error Tolerance
X
When using in infrared data transfer mode, set baud rate generator control register 0 (BRGC0)
to 10H.
: Main system clock oscillation frequency
0
0
Table 14-6. Relationship Between Main System Clock and Baud Rate
(% of Bit Rate)
131031 bps
f
X
+/– 0.87
= 8.3886 MHz
D0
1
1
X
Table 14-7. Bit Rate and Pulse Width Values
= 7.3728 MHz
D1
0
0
CHAPTER 14 SERIAL INTERFACE UART0
125000 bps
Pulse Width Minimum Value
f
X
= 8.000 MHz
D2
User’s Manual U14260EJ4V0UD
1
1
( s)
1.41
Note 2
D3
UART frame
0
0
Data bits
Data bits
IR frame
115200 bps
f
X
D4
= 7.3728 MHz
0
0
D5
1
1
3/16 Pulse Width
<Nominal Value>
1.63
( s)
78125 bps
f
D6
X
1
1
= 5.000 MHz
Pulse width =
3/16 bit time
D7
0
0
Maximum Pulse Width
Stop bit
Stop bit
65536 bps
f
1
1
X
= 4.1943 MHz
2.71
( s)
265

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