UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 433

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

<R>
Maskable interrupt request
Non-maskable interrupt request
Reset
: Don’t care
(c) Release by reset (reset by RESET pin, reset by WDT)
When a reset signal is generated, HALT mode is released, and the reset operation is carried out after the
lapse of oscillation stabilization time.
Remarks 1. f
Release Source
Reset signal
CPU status
Clock
Table 21-2. Operation in Response to Interrupt Request in HALT Mode
2. Values in parentheses are for operation with f
Operating
X
: Main system clock oscillation frequency
mode
HALT instruction
Figure 21-3. HALT Mode Release by Reset
MK
—
—
0
0
0
0
0
1
CHAPTER 21 STANDBY FUNCTION
HALT mode
Oscillation
User’s Manual U14260EJ4V0UD
PR
—
—
0
0
1
1
1
Oscillation
stop
Reset
period
IE
0
1
0
1
Oscillation stabilization
wait status
(2
X
17
= 8.38 MHz.
Oscillation
/f
ISP
X
1
0
1
Wait
: 15.6 ms)
Next address instruction execution
Interrupt servicing execution
Next address instruction execution
Interrupt servicing execution
HALT mode hold
Interrupt servicing execution
Reset processing
Operating mode
Operation
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