UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 258

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

256
TXE0
0
1
1
The relationship between the register settings and pins is shown below.
Note Can be set as port function.
Remark
The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock.
• Transmit/receive clock generation for baud rate by using main system clock
The main system clock is divided to generate the transmit/receive clock. The baud rate generated from the
main system clock is determined according to the following formula.
[Baud rate] =
f
n:
k:
X
RXE0
: Main system clock oscillation frequency
1
0
1
When ASCK0 is selected as the source clock of the 5-bit counter, substitute the input clock frequency
to the ASCK0 pin for f
Value set via TPS00 to TPS02 (0
Value set via MDL00 to MDL03 (0
PM
PS01
: don’t care, ASIM0: Asynchronous serial interface mode register 0,
Table 14-2. Relationship Between Register Settings and Pins (UART Mode)
0/1
0/1
0/1
: Port mode register, P
2
PS00
n+1
0/1
0/1
0/1
ASIM0
(k + 16)
f
X
CL0
0/1
0/1
0/1
X
CHAPTER 14 SERIAL INTERFACE UART0
in the above expression.
[Hz]
SL0
0/1
0/1
User’s Manual U14260EJ4V0UD
ISRM0 IRDAM0
0/1
0/1
: Port output latch
n
k
7, see Figure 14-5)
14, see Figure 14-5)
0
0
0
PM23 P23 PM24 P24
Note
1
1
Note
Note
0
0
Note
0
0
Transmission/reception RxD0
Operation Mode
Transmission
Reception
RxD0
RxD0
P23/
Pin Function
P23
TxD0
TxD0
TxD0
P24/
P24