UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 255

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UPD78F0078GK-9ET-A

Manufacturer Part Number
UPD78F0078GK-9ET-A
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0078GK-9ET-A

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Address: FFA2H After reset: 00H
Cautions 1. Writing to BRGC0 during a communication operation may cause abnormal output from the
Remarks 1. f
Symbol
BRGC0
2. f
3. n:
4. k:
5. The equation for the baud rate is as follows.
2. Set BRGC0 to 10H when using in infrared data transfer mode.
MDL03
TPS02
Figure 14-5. Format of Baud Rate Generator Control Register 0 (BRGC0)
[Baud rate] =
baud rate generator and disable further communication operations. Therefore, do not write
to BRGC0 during a communication operation.
X
SCK0
7
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
:
: Source clock for 5-bit counter
Main system clock oscillation frequency
Value set via TPS00 to TPS02 (0
Value set via MDL00 to MDL03 (0
MDL02
TPS02
TPS01
6
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2
n+1
CHAPTER 14 SERIAL INTERFACE UART0
(k + 16)
f
X
R/W
MDL01
TPS01
TPS00
5
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
User’s Manual U14260EJ4V0UD
[Hz]
External clock input to ASCK0
f
f
f
f
f
f
f
X
X
X
X
X
X
X
MDL00
TPS00
/2
/2
/2
/2
/2
/2
/2
2
3
4
5
6
7
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Source clock selection for 5-bit counter
n
k
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
Setting prohibited
Output clock selection for baud rate generator
SCK0
SCK0
SCK0
SCK0
SCK0
SCK0
SCK0
SCK0
SCK0
SCK0
SCK0
SCK0
SCK0
SCK0
SCK0
MDL03
7)
14)
3
/16
/17
/18
/19
/20
/21
/22
/23
/24
/25
/26
/27
/28
/29
/30
MDL02
2
MDL01
1
MDL00
0
10
11
12
13
14
n
0
1
2
3
4
5
6
7
k
0
1
2
3
4
5
6
7
8
9
253

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