UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 363

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

18.5.14 Other cautions
released) to a master device communication mode, first generate a stop condition to release the bus, then perform
master device communication.
been released (when a stop condition has not been detected).
Note The communication reservation operation executes a write to IIC shift register 0 (IIC0) when a stop condition
Remark STT0:
After a reset, when changing from a mode in which no stop condition has been detected (the bus has not been
When using multiple masters, it is not possible to perform master device communication when the bus has not
Use the following sequence for generating a stop condition.
(a) Set IIC transfer clock select register 0 (IICCL0).
(b) Set (1) bit 7 (IICE0) of IIC control register 0 (IICC0).
(c) Set (1) bit 0 (SPT0) of IICC0.
(Communication reservation)
interrupt request occurs.
MSTS0: Bit 7 of IIC status register 0 (IICS0)
IIC0:
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
Bit 1 of IIC control register 0 (IICC0)
IIC shift register 0
Figure 18-20. Communication Reservation Protocol
Yes
Note
Cancel communication
reservation
Define communication
reservation
MOV IIC0, #
MSTS0 = 0?
SET1 STT0
Wait
User’s Manual U14260EJ4V0UD
DI
EI
No
(Generate start condition)
H
Sets STT0 flag (communication reservation)
Defines that communication reservation is in effect
(defines and sets user flag to any part of RAM)
Secures wait period set by software (see Table 18-5).
Confirmation of communication reservation
Clear user flag
IIC0 write operation
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