UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 176

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

174
PRM0n
TMC0n
CRC0n
TOC0n
Cautions 1. CR00n and CR01n values in the following range should be set to:
Remarks 1.
ES11n
0/1
7
0
7
0
7
0
2. n = 0, 1
2. The cycle of the pulse generated via PPG output (CR00n setting value + 1) has a duty of
ES10n
0/1
6
0
6
0
0000H
(CR01n setting value + 1)/(CR00n setting value + 1).
6
0
: Don’t care
ES01n
Figure 8-34. Control Register Settings for PPG Output Operation
0/1
5
0
5
0
5
0
CR01n < CR00n
TOC04n
ES00n
0/1
CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01
4
0
(c) 16-bit timer output control register 0n (TOC0n)
1
4
0
(a) 16-bit timer mode control register 0n (TMC0n)
(b) Capture/compare control register 0n (CRC0n)
TMC0n3
LVS0n
0/1
(d) Prescaler mode register 0n (PRM0n)
3
0
1
3
0
CRC02n
TMC0n2
LVR0n
0/1
1
0
2
0
User’s Manual U14260EJ4V0UD
TOC01n
CRC01n CRC00n
PRM01n
FFFFH
0/1
1
0
1
OVF0n
TOE0n
PRM00n
0/1
0
1
0
CR00n used as compare register
CR01n used as compare register
Enables TO0n output.
Reverses output on match between TM0n and CR00n.
Specifies initial value of TO0n output F/F (setting
Reverses output on match between TM0n and CR01n.
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Clears and starts on match between TM0n and CR00n.
“11”
is prohibited).