UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 160

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

8.4 Operation of 16-Bit Timer/Event Counters 00, 01
8.4.1 Interval timer operation
in Figure 8-15 allows operation as an interval timer.
(CR00n) beforehand as the interval.
the TM0n value cleared to 0 and the interrupt request signal (INTTM00n) is generated.
mode register 0n (PRM0n).
158
Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown
The basic operation setting procedure is as follows.
<1> Set the CRC0n register (see Figure 8-15 for the set value).
<2> Set any value to the CR00n register.
<3> Set the count clock by using the PRM0n register.
<4> Set the TMC0n register to start the operation (see Figure 8-15 for the set value).
Remark For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS.
Interrupt requests are generated repeatedly using the count value set in 16-bit timer capture/compare register 00n
When the count value of 16-bit timer counter 0n (TM0n) matches the value set to CR00n, counting continues with
The count clock of the 16-bit timer/event counter can be selected using bits 0 and 1 (PRM00n, PRM01n) of prescaler
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the
Setting
CRC0n
TMC0n
PRM0n
n = 0, 1
7
0
7
0
description of the respective control registers for details.
ES11n
0/1
Figure 8-15. Control Register Settings for Interval Timer Operation
6
0
6
0
ES10n
0/1
CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01
(a) 16-bit timer mode control register 0n (TMC0n)
5
0
5
0
(b) Capture/compare control register 0n (CRC0n)
ES01n
0/1
(c) Prescaler mode register 0n (PRM0n)
4
0
4
0
ES00n
0/1
TMC0n3
3
0
1
User’s Manual U14260EJ4V0UD
3
0
CRC02n
TMC0n2
0/1
1
2
0
CRC01n
0/1
1
0
PRM01n
0/1
CRC00n
OVFn0
0
0
PRM00n
0/1
CR00n used as compare register
Clears and starts on match between TM0n and CR00n.
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)