UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 431

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

21.2 Standby Function Operations
21.2.1 HALT mode
(1) HALT mode setting and operating statuses
Clock generator
CPU
Ports (output latches) Status before HALT mode setting is held.
16-bit timer/event
counters 00, 01
8-bit timer/event
counters 50, 51
Watch timer
Watchdog timer
Clock output
Buzzer output
A/D converter
Serial interface
External interrupt
Bus line
during
external
expansion
Item
Notes 1. Including case when external clock is not supplied.
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the
subsystem clock.
The operating statuses in the HALT mode are described below.
HALT Mode
2. Including case when external clock is supplied.
AD0 to AD7 High impedance
A8 to A15 Status before HALT mode setting is held.
ASTB
WR, RD
WAIT
Setting
Both main system clock and subsystem clock can be oscillated. Clock supply to CPU stops.
Operation stops.
Operable
Operable
Operable when f
selected as count clock
Operable
Operable when f
selected as output clock
Operable
Stop
Operable
Operable
Low level
High level
High impedance
Without subsystem
clock
Note 1
HALT Instruction Execution when
Using Main System Clock
Table 21-1. HALT Mode Operating Statuses
X
to f
X
/2
CHAPTER 21 STANDBY FUNCTION
X
7
/2
is
7
is Operable
User’s Manual U14260EJ4V0UD
Operable
clock
With subsystem
Note 2
Operation stops.
With main system
clock oscillation
HALT Instruction Execution when
Using Subsystem Clock
Stop
Operable when TI50,
TI51 are selected as
count clock.
Operable when f
selected as count clock.
Operable when f
selected as output clock.
BUZ is at low level.
Operable during
external clock input.
With main system
clock oscillation
stopped
XT
XT
is
is
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