UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 318

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(2) Transfer start
(3) Communication operations
(4) Transfer completion
316
A serial transfer starts when the following two conditions have been satisfied and transfer data has been set (or
read) to serial I/O shift register 3 (SIO3).
<Transfer start conditions>
• SIO3 operation control bit (CSIE3) = 1
• After an 8-bit serial transfer, either the internal serial clock is stopped or SCK3 is set to high level.
<Transfer start timing>
• Transmit/transmit and receive mode (MODE3 = 0)
• Receive-only mode (MODE3 = 1)
Caution
In the 3-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is transmitted or
received in synchronization with the serial clock.
Serial I/O shift register 3 (SIO3) is shifted in synchronization with the falling edge of the serial clock. Transmission
data is held in the SO3 latch and is output from the SO3 pin. Data that is received via the SI3 pin in synchronization
with the rising edge of the serial clock is latched to SIO3.
Completion of an 8-bit transfer automatically stops the serial transfer operation and the interrupt request flag
(CSIIF3) is set.
Transfer starts when writing to SIO3.
Transfer starts when reading from SIO3.
After data has been written to SIO3, transfer will not start even if the CSIE3 bit value is set
to 1.
CSIIF3
SCK3
SO3
SI3
Figure 16-4. Timing of 3-Wire Serial I/O Mode
Transfer starts in synchronization with the SCK3 falling edge
Latched to SIO3 at the SCK3 rising edge
1
CHAPTER 16 SERIAL INTERFACE SIO3
DO7 DO6 DO5 DO4 DO3 DO2 DO1
DI7
2
DI6
User’s Manual U14260EJ4V0UD
3
DI5
4
DI4
5
DI3
6
DI2
7
DI1
Transfer completion
8
DO0
DI0