UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 362

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

SDA0
SCL0
is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IIC control register 0 (IICC0) to 1
before a stop condition is detected.
360
Remark IIC0:
Communication reservations are accepted via the following timing. After bit 1 (STD0) of IIC status register 0 (IICS0)
Figure 18-20 shows the communication reservation protocol.
Hardware processing
1
Program processing
2
STT0: Bit 1 of IIC control register 0 (IICC0)
STD0: Bit 1 of IIC status register 0 (IICS0)
SPD0: Bit 0 of IIC status register 0 (IICS0)
SDA0
SPD0
STD0
SCL0
3
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
IIC shift register 0
Figure 18-19. Timing for Accepting Communication Reservations
4
Communication
reservation
STT0 = 1
Figure 18-18. Communication Reservation Timing
5
6
7
User’s Manual U14260EJ4V0UD
8
Standby mode
Output by master with bus mastership
9
Set SPD0
and INTIIC0
Write to
IIC0
Set
STD0
1
2
3
4
5
6