UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 593

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2nd
Edition
Modification of Figure 15-1 Block Diagram of Serial Interface UART2
Shift of descriptions about asynchronous serial interface status register 2 (ASIS2)
and asynchronous serial interface transmit status register 2 (ASIF2) from 15.3
Registers to Control Serial Interface UART2 to 15.2 Configuration of Serial
Interface UART2
Modification of Caution 1 and addition of Cautions 2 and 3 in Figure 15-4
Format of Asynchronous Serial Interface Transmit Status Register 2 (ASIF2)
Addition of Notes 7 and 8 in Figure 15-8 Format of Transfer Mode
Specification Register 2 (TRMC2)
Modification of error values in Table 15-2 Relationship Between Main System
Clock and Baud Rate
Addition of Caution in Table 15-3 Maximum Permissible Baud Rate Error and
Minimum Permissible Baud Rate Error
Modification of the INTST2 timing in (ii) and (iii) of Figure 15-12 Timing of
Asynchronous Serial Interface Transmit Completion Interrupt Request
Division of Table 15-6 Transmission Status and Writing to TXB2 in the
previous edition into Table 15-4 Writing to TXBF and TXB2 (When Successive
Transmission Is Started) and Table 15-5 Writing to TXSF and TXB2 (When
Successive Transmission Is in Progress)
Modification of Figure 15-14 Timing of Starting Successive Transmission
Modification of Figure 15-15 Timing of Completing Successive Transmission
Modification of Figure 15-17 Receive Error Timing
Addition of Table 15-10 Register Settings
Modification of Figure 16-1 Block Diagram of Serial Interface SIO3
Addition of Notes 3 and 4 in Figure 16-2 Format of Serial Operation Mode
Register 3 (CSIM3)
Addition of Table 16-2 Register Settings
Modification of Figure 17-1 Block Diagram of Serial Interface CSI1
Addition of description about SS1 pin in 17.4.2 (2) Communication operation
Modification of Figure 17-6 Timing of 3-Wire Serial I/O Mode
Modification of Figure 17-8 Output Operation of First Bit
Modification of Figure 17-9 Output Value of SO1 Pin (Last Bit)
Deletion of 17.4.2 (6) SCK1 pin and (7) SO1 pin in the previous edition
Addition of Table 17-2 Register Settings
Modification of Figure 18-1 Block Diagram of Serial Interface IIC0
Incorporation of 18.3 (4) IIC shift register 0 (IIC0) and (5) Slave address
register 0 (SVA0) in the previous edition into 18.2 (1) IIC shift register 0 (IIC0)
and (2) Slave address register 0 (SVA0), respectively
Addition of description to “Transfer Lines” in Figure 18-16 Wait Signal
Addition of descriptions to Notes 1 and 2 in Table 18-2 INTIIC0 Timing and Wait
Control
Modification of Figure 18-21 Master Operation Flowchart and Figure 18-22
Slave Operation Flowchart
APPENDIX E REVISION HISTORY
Contents
User’s Manual U14260EJ4V0UD
CHAPTER 15 SERIAL
INTERFACE UART2
CHAPTER 16 SERIAL
INTERFACE SIO3
CHAPTER 17 SERIAL
INTERFACE CSI1
CHAPTER 18 SERIAL
INTERFACE IIC0
( PD780078Y SUBSERIES
ONLY)
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