PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 104

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Transmission via this register is possible even when the transmitter is in XOFF state
(however, CTS must be ‘low’).
The ’TIC’ value is an eight-bit value. The number of significant bits is determined by the
programmed asynch character length via bit field ’CHL’ in register
(if programmed) and selected number of stop bits are automatically appended, equal to
the characters provided via the transmit data buffer. The usage of ’TIC’ is independent
of in-band flow control mechanism, i.e. is not affected by bit ’FLON’ in register
anyway.
To control multiple accesses to register
Executing) is provided which signals that the transmission command of currently
programmed ’TIC’ is accepted but not yet completely executed. Further access to
register
4.4.4.3
Transmitter:
The transmitter output is enabled if CTS signal is ‘LOW’ AND the XON state is reached
in case of in-band flow control is enabled. If the in-band flow control is disabled
(
Nevertheless setting bit
independent of the condition of the CTS signal, the in-band flow control (XON/XOFF)
mechanism would still be operational if enabled via bit
Receiver:
For some applications it is desirable to provide means of out-of-band flow control to
indicate to the far end transmitter that the local receiver’s buffer is getting full.
This flow control can be used between two DTEs as shown in
DTE and a DCE (MODEM) as shown in
flow control.
Setting bit
control for the receiver. When the shadow part of the receive FIFO has reached a set
threshold of 28 bytes, the RTS signal is forced inactive (high). When the shadow part of
the receive FIFO is empty, the RTS is re-asserted (low). Note that the data is
immediately transferred from the shadow receive FIFO to the user accessible RFIFO (as
long as there is space available). So when the shadow receive FIFO reaches the 28
bytes threshold, there is 4 more byte storage available before overflow can occur. This
allows sufficient time for the far end transmitter to react to the change in the RTS signal
and stop sending more data.
Figure 50
A (SCC) feeds the CTS input of the second DTE-B (another SCC). For example while
Data Sheet
CCR2H
TICR
:FLON = ‘0’), the transmitter is only controlled by the CTS signal.
shows the connection between two SCC devices as DTEs. The RTS of DTE-
Out-of-band Flow Control
CCR1H
is only allowed if bit
:FRTS = ‘1’ and
CCR1H
:FCTS = ‘1’ allows the transmitter to send data
STARL
CCR1H
Figure 51
TICR
:TEC is ‘0’ again.
104
, an additional status bit
:RTS = ‘0’ invokes this out-of-band flow
that supports this kind of bi-directional
CCR2H
Detailed Protocol Description
Figure 50
:FLON = ‘1’.
CCR3L
STARL
and between a
. Parity value
PEB 20542
PEF 20542
2000-09-14
:TEC (TIC
CCR2H