PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 239

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

5.2.3
Each register description is organized in three parts:
• a head with general information about reset value, access type (read/write), channel
• a table containing the bit information (name of bit positions);
• a section containing the detailed description of each bit.
Register 86
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 87
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Data Sheet
Bit
Bit
specific offset address and usual handling;
15
7
Channel Specific DMA Registers
Primary Transmit Base Address (Low Byte)
Primary Transmit Base Address (Mid Byte)
TBADDR1L
TBADDR1M
14
6
read/write
00
Channel A
B0
written by CPU, evaluated by SEROCCO-D
read/write
00
Channel A
B1
written by CPU, evaluated by SEROCCO-D
H
H
H
H
13
5
Channel B
CA
Channel B
CB
H
H
TBADDR1(15:8)
TBADDR1(7:0)
12
4
239
11
3
10
2
Register Description
1
9
PEB 20542
PEF 20542
2000-09-14
0
8