PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 94

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

4.1.8
In HDLC/SDLC mode, error protection is done by CRC generation and checking.
In standard applications, CRC-CCITT algorithm is used. The Frame Check Sequence at
the end of each frame consists of two bytes of CRC checksum.
If required, the CRC-CCITT algorithm can be replaced by the CRC-32 algorithm,
enabled via bit ’C32’ in register CCR1L. In this case the Frame Check Sequence
consists of four bytes.
Optionally the internal handling of received and transmitted CRC checksum can be
influenced via control bits ’RCRC’, ’DRCRC’ in register
CCR2H.
Receive direction:
If not disabled by setting bit ’DRCRC’ (register CCR3H), the received CRC checksum is
always assumed to be in the 2 (CRC-CCITT) or 4 (CRC-32) last bytes of a frame,
immediately preceding a closing flag. If bit ’RCRC’ is set, the received CRC checksum
is treated as data and will be forwarded to the RFIFO, where it precedes the frame status
byte. Nevertheless the received CRC checksum is additionally checked for correctness.
If CRC checking is disabled with bit CCR3H:DRCRC, the limits for ‘Valid Frame’ check
are modified accordingly (refer to description of the Receive Status Byte, RSTA:VFR).
Transmit direction:
If bit ’XCRC’ is set, the CRC checksum is not generated internally. The checksum has to
be provided via the transmit data buffer by software. The transmitted frame will only be
closed automatically with a (closing) flag.
Note: The SCC does not check whether the length of the frame, i.e. the number of bytes,
4.1.9
The SCC offers the possibility to supervise the maximum length of received frames and
to terminate data reception in the case that this length is exceeded.
This feature is controlled via the special Receive Length Check Registers RLCRL/
RLCRH.
The function is enabled by setting bit ’RCE’ (Receive Length Check Enable) and the
maximum frame length to be checked is programmed via bit field ’RL’. The maximum
receive length can be determined as a multiple of 32-byte blocks as follows:
MAX_LENGTH = (RL + 1) ´ 32 ,
where RL is the value written to bit field ’RL’. Thus, the maximum length of receive
frames can be programmed between 32 and 65536 bytes.
All frames exceeding this length are treated as if they had been aborted by the remote
station, i.e. the CPU is informed via
Data Sheet
to be transmitted makes sense or not according the HDLC protocol.
CRC Generation and Checking
Receive Length Check Feature
94
Detailed Protocol Description
CCR3H
and ’XCRC’ in register
PEB 20542
PEF 20542
2000-09-14