PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 45

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

3.2.2.1
The SCC transmit FIFO is divided into two parts of 32 bytes each (’transmit pools’). The
interface between the two parts provides synchronization between the microprocessor
accesses and the protocol logic working with the serial transmit clock.
Figure 8
A 32 bytes FIFO part is accessable by the CPU/DMA controller; it accepts transmit data
even if the SCC is in power-down condition (register
The only exception is a transmit data underrun (XDU) event. In case of an XDU event
(e.g. after excessive bus latency), the FIFO will neither accept more data nor transfer
another byte to the protocol logic. This XDU blocking mechanism prevents unexpected
serial data. The blocking condition must be cleared by reading the interrupt status
register
should not be masked in register IMR1.
Transfer of data to the 32 byte shadow part only takes place if the SCC is in power-up
condition and an appropriate transmit clock is provided depending on the selected clock
mode.
Serial data transmission will start as soon as at least one byte is transferred into the
shadow FIFO and transmission is enabled depending on the selected clock mode (CTS
signal active, clock strobe signal active, timeslot valid or clock gapping signal inactive).
3.2.2.2
The SCC receive FIFO is divided into two parts of 32 bytes each. The interface between
the two parts provides synchronization between the microprocessor accesses and the
protocol logic working with the serial receive clock.
Data Sheet
ISR1
SCC Transmit FIFO
SCC Receive FIFO
after the XDU interrupt was generated. Thus, the XDU interrupt indication
SCC Transmit FIFO
(not accessable by CPU)
32 byte Transmit Pool
(accessable by CPU)
32 byte Shadow part
45
CCR0H
bit PU=’0’).
Functional Overview
PEB 20542
PEF 20542
2000-09-14