PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 212

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
AMRAH2
AMRAL2
AMRAH1
AMRAL1
Receive Mask Address 2 Byte High
Receive Mask Address 2 Byte Low
Receive Mask Address 1 Byte High
Receive Mask Address 1 Byte Low
Setting a bit in this registers to ’1’ masks the corresponding bit in
registers RAH2/RAL2/RAH1/RAL1. A masked bit position always
matches when comparing the received frame address with registers
RAH2/RAL2/RAH1/RAL1, allowing extended broadcast mechanism.
bit = ’0’
bit = ’1’
The dedicated bit position is NOT masked. This bit
position in the received address must match with the
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1
The dedicated bit position is masked. This bit position in
the received address NEED NOT match with the
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1
to accept the frame.
to accept the frame.
5-212
Register Description (AMRAH2)
(hdlc modes)
(hdlc modes)
(hdlc modes)
(hdlc modes)
PEB 20542
PEF 20542
2000-09-14