PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 128

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PEB 20542 F V1.3

Manufacturer Part Number
PEB 20542 F V1.3
Description
IC CTRLR DMA SERIAL 2-CH TQFP144
Manufacturer
Infineon Technologies
Series
SEROCCO™r
Datasheet

Specifications of PEB 20542 F V1.3

Function
Serial Optimized Communications Controller
Interface
HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-LFQFP
Includes
Bit Processor Functions, Serial Communication Controllers (SCCs)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB20542FV1.3X
SP000007633
Data Sheet
OSCPD
BRC
DSHP
Oscillator Power Down
Setting this bit to ’0’ enables the internal oscillator. For power saving
purposes (escpecially if clock modes are used which do not need the
internal oscillator) this bit may remain set to ’1’.
OSCPD=’0’
OSCPD=’1’
Note: After reset this bit is set to ’1’, i.e. the oscillator is in power down
Bus Request Pin Characteristic
This bit controls the characteristic of output pin BREQ:
BRC=’0’
BRC=’1’
Note: If bus preemption as shown in
Disable Shaper
This bit has to be set to ’0’ if the shaping function in the oscillator unit is
desired. The shaper amplifies the oscillator signal and improves the
slope of the clock edges.
DSHP=’0’
DSHP=’1’
Note: After reset this bit is set to ’1’, i.e. the shaper is disabled!
mode!
enabling the push/pull output characteristic makes a strong pull-up
resistor for pin BREQ obsolete.
The internal oscillator is active.
The internal oscillator is in power down mode.
Open Drain active low (reset value)
Push/Pull active low
Shaper is enabled. Recommended setting if a crystal is
connected to pins XTAL1/XTAL2.
Shaper is disabled (bypassed). Recommended setting if
- a TTL level clock signal is supplied to pin XTAL1
- the oscillator unit is unused
5-128
Register Description (GMODE)
Chapter 3.4.3
is not needed,
PEB 20542
PEF 20542
2000-09-14

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