PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 161

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
DIV
ODS
ICD
RTS
Data Inversion
This bit is only valid if NRZ data encoding is selected via bit field SC(2:0)
in register CCR0H.
DIV=’0’
DIV=’1’
Output Driver Select
The transmit data output pin TxD can be configured as push/pull or open
drain output chracteristic.
ODS=’0’
ODS=’1’
Invert Carrier Detect Pin Polarity
ICD=’0’
ICD=’1’
Request To Send Pin Control
The request to send pin RTS can be controlled by SEROCCO-D as an
output autonomously or via setting/clearing bit ’RTS’.
This bit is not valid in clock mode 4.
RTS=’0’
RTS=’1’
No Data Inversion.
Data is transmitted/received inverted (on a per bit basis).
In HDLC and HDLC Synchronous PPP modes the
continuous ’1’ idle sequence is NOT inverted. Thus it is
recommended to select the flag sequence for interframe
time fill transmission (CCR2H:ITF = ’1’), which is inverted.
TxD pin is open drain output.
TxD pin is push/pull output.
Carrier Detect (CD) input pin is active high.
Carrier Detect (CD) input pin is active low.
Pin RTS (output) pin is controlled by SEROCCO-D
autonomously.
HDLC Mode:
RTS is activated during transmission. In bus configuration
mode the functionality depends on bit field ’SOC’ setting.
Note: For autonomous RTS pin control a transmit clock is
ASYNC/BISYNC Mode:
The functionality depends on setting of bit ’FRTS’
Pin RTS can be controlled by software. The output level of
this pin depends on bit ’FRTS’.
necessary.
5-161
Register Description (CCR1H)
PEB 20542
PEF 20542
(all modes)
(all modes)
(all modes)
(all modes)
2000-09-14