PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 266

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

The data transmission flow, from the CPU’s point of view, is outlined in
Figure 63
6.3.2
The receive DMA controller has to be prepared by writing an appropriate address to its
RBADDR1L/M/H registers and the maximum buffer size to register
a new packet is received by the SCC, the DMA controller will request the external bus
and then move receive data out of the RFIFO. The receive data is directly written on the
external bus, beginning at address RBADDR1.
Now the DMA has to face two possible scenarios:
• If the maximum buffer size programmed in register
Data Sheet
transferred, DMA transfer stops and a Receive Buffer Full (RBF) interrupt is
generated. The CPU now updates the receive buffer base address in the appropriate
registers RBADDR1L/M/H and restarts the DMA receiver by setting the ’RE’ bit in
register RMBSH. Optionally the maximum buffer size value can be updated with the
same register write access.
reads <XBC> bytes
of transmit data
DMA Controller
Data Reception (DMA Controlled)
DMA Controlled Data Transmission (Flow Diagram)
(register XBC1L/H)
Set Tx Byte Count
('XBC') and issue
'TDTE' Interrupt
command
'XF'
No
No
Set TxBuffer Base
(TBADDR1H/M/L)
register GMODE)
(set bit 'IDMA' in
End of Message
Data available
Enable DMA
in TxBuffer
Transmit
TX DMA
Address
READY
START
266
Yes
?
?
Yes
RMBSL/RMBSH
(register XBC1L/H)
Set Tx Byte Count
('XBC') and issue
'TDTE' Interrupt
'XF'+'XME'
command
RMBSL/RMBSH
Figure
bytes of transmit
data (incl. end of
DMA Controller
Programming
reads <XBC>
Action taken
by CPU
Interrupt
indication to CPU
Action taken by
internal DMA
message)
PEB 20542
PEF 20542
2000-09-14
has been
67.
. If