PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 9

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

List of Figures
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Data Sheet
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Point-to-Point Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Point-to-Multipoint Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 26
Multimaster Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pin Configuration P-TQFP-144-10 Package . . . . . . . . . . . . . . . . . . . . 28
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
XFIFO/RFIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . 47
XFIFO/RFIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . . 47
Clock Supply Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Clock Mode 0a/0b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Clock Mode 1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Clock Mode 2a/2b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Clock Mode 3a/3b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Clock Mode 4 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Selecting one time-slot of programmable delay and width . . . . . . . . . 58
Selecting one or more time-slots of 8-bit width . . . . . . . . . . . . . . . . . . 60
Clock Mode 5a Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Clock Mode 5a "Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Clock Mode 5a "Non Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . 63
Selecting one or more octet wide time-slots . . . . . . . . . . . . . . . . . . . . 65
Clock Mode 5b Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Clock Mode 6a/6b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Clock Mode 7a/7b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enabled) . . . 71
DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Disabled) . . . 71
DPLL Algorithm for FM0, FM1 and Manchester Encoding . . . . . . . . . 72
Request-to-Send in Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
NRZ and NRZI Data Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
FM0 and FM1 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Manchester Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SCC Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SEROCCO-D requests and gets the bus. . . . . . . . . . . . . . . . . . . . . . . 82
Un-interrupted Series of 32 DMA Bus Cycles . . . . . . . . . . . . . . . . . . . 82
Bus Preemption and Re-gain of Bus Control . . . . . . . . . . . . . . . . . . . . 83
SEROCCO-D requests and gets the bus. . . . . . . . . . . . . . . . . . . . . . . 83
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
HDLC Receive Data Processing in 16 bit Automode . . . . . . . . . . . . . . 89
HDLC Receive Data Processing in 8 bit Automode . . . . . . . . . . . . . . . 89
9
PEB 20542
PEF 20542
2000-09-14
Page