PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 263

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

6.3
The following table provides a definition of terms used in this chapter to describe the
operation of the DMA controller.
Table 17
Packet
Buffer
Block
Bus Cycle
DMA Transfer
6.3.1
Standard Transfer Mode:
Any packet transmission is prepared by writing the transmit buffer start address into
registers TBADDR1L/M/H and the packet size in number of bytes to registers XBC1L/
XBC1H.
Now there are two possible scenarios:
• If the prepared transmit buffer in memory contains a complete packet, the start
Data Sheet
command for DMA transmission is issued by setting bits ’XF’ and ’XME’ in register
XBC1H
data beginning at address TBADDR1. The data is immediately transferred into the
XFIFO. After the last byte has been transmitted, the protocol machine appends the
to ’1’. The DMA controller will request the external bus and then read transmit
Internal DMA Mode
Data Transmission (DMA Controlled)
DMA Terminology
A "Packet" is a connected block of data bytes. This can be
an HDLC/PPP frame as well as a number of ASYNC/
BISYNC characters up to a specific limit (received
termination character, CMDRH:RFRD command). If a
receive status byte (RSTA) is attached to data bytes, it is
also considered as part of the packet.
A "Buffer" is a limited space in memory that is reserved for
DMA reception/transmission. Every time the DMA
controller completes a buffer transfer, it notifies the CPU
with an appropriate interrupt.
A packet can go into one single buffer, or it can go
fragmented into multiple buffers.
A "Block" is the amount of data that is transfered from the
memory to the XFIFO (transmit DMA transfer) or from the
RFIFO to the memory. In HDLC/PPP modes the block size
is 32 bytes by default. It can be lowered with the receive
FIFO threshold in register CCR3H, bit field ’RFTH(1..0)’.
A "Bus Cycle" corresponds to a single byte/word transfer.
Multiple bus cycles make up a block transfer.
A "DMA Transfer" is the movement of complete buffers
and/or packets between the XFIFO/RFIFO and the
memory.
263
Programming
PEB 20542
PEF 20542
2000-09-14