PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 74

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

HDLC/SDLC: Transmission will be initiated again by the SCC as soon as possible if the
first part of the frame is still present in the SCC transmit FIFO. If not, an XMR interrupt is
generated.
Since a ‘zero’ (‘low’) on the bus prevails over a ‘1’ (high impedance) if a wired-OR
connection is implemented, and since the address fields of the HDLC frames sent by
different stations normally differ from one another, the fact that a collision has occurred
will be detected prior to or at the latest within the address field. The frame of the
transmitter with the highest temporary priority (determined by the address field) is not
affected and is transmitted successfully. All other stations cease transmission
immediately and return to bus monitoring state.
Note: If a wired-OR connection has been realized by an external pull-up resistor without
3.2.10
To ensure that all competing stations are given a fair access to the transmission medium,
a two-stage bus access priority scheme is supported by SEROCCO-D:
Once a station has successfully completed the transmission of a frame, it is given a lower
level of priority. This priority mechanism is based on the requirement that a station may
attempt transmitting only when a determined number of consecutive ‘1’s are detected on
the bus.
Normally, a transmission can start when eight consecutive ‘1’s on the bus are detected
(through pin CxD). When an HDLC frame has been successfully transmitted, the internal
priority class is decreased. Thus, in order for the same station to be able to transmit
another frame, ten consecutive ‘1’s on the bus must be detected. This guarantees that
the transmission requests of other stations are satisfied before the same station is
allowed a second bus access. When ten consecutive ‘1’s have been detected,
transmission is allowed again and the priority class (of all stations) is increased (to eight
‘1’s).
Inside a priority class, the order of transmission (individual priority) is based on the HDLC
address, as explained in the preceding paragraph. Thus, when a collision occurs, it is
always the station transmitting the only ‘zero’ (i.e. all other stations transmit a ‘one’) in a
bit position of the address field that wins, all other stations cease transmission
immediately.
Data Sheet
decoupling, the data output (TxD) can be used as an open drain output and
connected directly to the CxD input.
For correct identification as to which frame is aborted and thus has to be repeated
after an XMR interrupt has occurred, the contents of SCC transmit FIFO have to
be unique, i.e. SCC transmit FIFO should not contain data of more than one frame.
For this purpose new data may be provided to the transmit FIFO only after ’ALLS’
interrupt status is detected.
Serial Bus Access Priority Scheme
74
Functional Overview
PEB 20542
PEF 20542
2000-09-14