PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 248

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Register 98
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Data Sheet
RBADDR1
(23:0)
Bit
7
Primary Receive Base Address
Only valid in internal DMA controller modes.
This bit field determines the base address of the primary DMA receive
buffer (buffer 1).
• If single-buffer operation is selected, this base address is the only one
• If switched-buffer operation is selected (refer to register DMODE),
Note: If 16-bit bus operation is selected, the base address must be word
used; the secondary base address RBADDR2(23:0) is "don’t care" in
this case.
reception takes place based on two receive buffers that are filled
alternating.
Primary Receive Base Address 1 (High Byte)
RBADDR1H
6
aligned, i.e. bit RBADDR1(0) must be set to ’0’.
read/write
00
Channel A
BE
written by CPU, evaluated by SEROCCO-D
H
H
5
Channel B
D8
H
RBADDR1(23:16)
4
248
3
2
Register Description
1
PEB 20542
PEF 20542
2000-09-14
0