PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 226

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
RME
TCD
RFS
TIME
Receive Message End Interrupt
This bit set to ’1’ indicates that the reception of one message is
completed, i.e. either
– one message which fits into RFIFO not exceeding the receive FIFO
– the last part of a message, all in all exceeding the receive FIFO
is stored in the RFIFO.
The complete message length can be determined by reading the RBCL/
RBCH
4, 2 or 1 least significant bits of register RBCL, depending on the
selected RFIFO threshold (bit field ’RFTH(1:0)’ in register CCR3H).
Additional frame status information is available in the
in the RFIFO as the last byte of each frame.
Note: After the RFIFO contents have been read, an CMDRH:RMC
Termination Character Detected Interrupt
This bit is set to ’1’, if a termination character (
in the receive data stream or an ’RFRD’ command, issued in the
register, has been completed. The SCC will insert a ’block end’ indication
to the RFIFO. The actual block length can be determined by reading
register
Note: After the RFIFO contents have been read, an CMDRH:RMC
Receive Frame Start Interrupt
This bit is set to ’1’, if the beginning of a valid frame is detected by the
receiver. A valid frame start is detected either if a valid address field is
recognized (in all operating modes with address recognition) or if a start
flag is recognized (in all operating modes with no address recognition).
Time Out Interrupt
This bit is set to ’1’, if the time out limit is exceeded, i.e. no new character
was received in a programmable period of time (refer to register
bit fields ’TOIE’ and ’TOLEN’ for more information).
threshold, or
threshold
command must be issued to free the RFIFO for new receive data.
command must be issued to free the RFIFO for new receive data.
registers. The number of bytes stored in RFIFO is given by the 5,
RBCL
.
5-226
Register Description (ISR2)
TCR
(async/bisync mode)
) has been detected
RSTA
(async mode)
PEB 20542
byte, stored
PEF 20542
(hdlc mode)
(hdlc mode)
2000-09-14
CMDRH
TOLEN