PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 107

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

while MONOSYNC uses only one SYN.
format.
Figure 52
The SYN character, its length, the length of data characters and additional parity
generation are programmable:
• 1 SYN character with 6 or 8 bit length (MONOSYNC), programmable via register
• 2 SYN characters with 6 or 8 bit length each (BISYNC), programmable via registers
• Data character length may vary from 5 to 8 bits (bit field ’CHL’ in register
• Parity information (even/odd parity, mark, space) may be appended to the character
4.5.2
The receiver is generally activated by setting bit ’RAC’ in register
the CD signal may be used to control data reception depending on the selected clock
mode. After issuing the HUNT command, the receiver monitors the incoming data
stream for the presence of specified SYN character(s). However, data reception is still
disabled. If synchronization is gained by detecting the SYN character(s), an SCD
interrupt is generated and all following data is pushed to the receive FIFO, i.e. control
sequences, data characters and optional CRC frame checking sequence (the LSB is
received first). In normal operation, SYN characters are excluded from storage to receive
FIFO. SYN character length can be specified independently of the selected data
character length. If required, the character parity bit and/or parity status is stored
together with each data byte in the receive FIFO.
As an option, the loading of SYN characters in receive FIFO may be enabled by setting
the bit ’SLOAD’ in register
data. Consequently, for correct operation it must be guaranteed that SYN character
Data Sheet
SYNCL
SYNCH/SYNCL
(bit ’PARE’ and bit field ’PAR’ in register
(SYNL)
2 Leading
SYN
Characters
SYN
.
Data Reception
(SYNH)
BISYNC Message Format
SYN
.
Start
of
Header
SOH
CCR3L
Header
. Note that in this case SYN characters are treated as
Start
of
Text
Figure 52
107
STX
CCR3H
Text
).
gives an example of the message
Detailed Protocol Description
(Data)
End
of
Text
CCR3L
ETX
. Additionally,
Frame
Checking
Sequence
PEB 20542
PEF 20542
CCR3L
CRC
2000-09-14
ITD01805
).