PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 81

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Table 10
BHE
1
1
Table 11
UDS
0
0
1
1
Each of the two serial channels of SEROCCO-D is controlled via an identical, but
completely independent register set (Channel A and B). Global functions that are
common to or independent from the two serial channels are located in global registers.
3.4
3.4.1
Every time SEROCCO-D needs to access the bus in order to DMA transfer receive data
from the RFIFO to host memory or transmit data from host memory to the XFIFO, it has
to request the bus arbiter for the bus mastership. This is achieved by asserting the open-
drain BREQ signal to low. When SEROCCO-D samples the bus grant (BGNT) active, it
Data Sheet
BLE
0
1
LDS
0
1
0
1
Internal DMA Controller
Arbitration for Bus Control
Data Bus Access 16-bit Intel Mode
Data Bus Access 16-bit Motorola Mode
Register Access
Byte access (8 bit), even address
no data transfer
Register Access
Word access (16 bit)
Byte access (8 bit), even address
Byte access (8 bit), odd address
no data transfer
81
Functional Overview
Data Pins Used
D(7:0)
-
Data Pins Used
D(15:0)
D(15:8)
D(7:0)
-
PEB 20542
PEF 20542
2000-09-14