PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 203

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
SRC
TMD
CNT(2:0)
Clock Source (valid in clock mode 5 only)
This bit selects the clock source of the internal timer:
SRC = ’0’
SRC = ’1’
Timer Mode
This bit must be set to ’1’ if HDLC Automode operation is selected. In all
other protocol modes it must remain ’0’:
TMD=’0’
TMD=’1’
Counter
The meaning of this bit field depends on the selected protocol mode.
In HDLC Automode, with bit TMD=’1’:
• Retry Counter (in HDLC protocol known as ’N2’):
In all other modes, with bit TMD=’0’:
• Restart Counter :
Bit field ’CNT’ indicates the number of S-Command frames (with poll
bit set) which are transmitted autonomously by SEROCCO-D after
every expiration of the time out period ’t’ (determined by ’TVALUE’), in
case an I-Frame gets not acknowledged by the opposite station. The
maximum value is 6 S-command frames. If ’CNT’ is set to ’7’, the
number of S-commands is unlimited in case of no acknowledgement.
Bit field ’CNT’ indicates the number of automatic restarts which are
performed by SEROCCO-D after every expiration of the time-out
period ’t’, in case the timer is not stopped by setting bit ’TRES’ in
register
to ’7’, a timer interrupt is generated periodically with time period ’t’
determined by bit field ’TVALUE’.
CMDRL
The timer is clocked by the effective transmit clock.
The timer is clocked by the frame-sync synchronization
signal supplied via the FSC pin in clock mode 5.
The timer is controlled by the CPU via access to registers
CMDRL
The timer can be started any time by setting bit ’STI’ in
register CMDRL. After the timer has expired it generates
a timer interrupt. The timer can be stopped any time by
setting bit ’TRES’ in register
The timer is used by the SEROCCO-D for protocol
specific time-out and retry transactions in HDLC
Automode.
to ’1’. The maximum value is 6 restarts. If ’CNT’ is set
and TIMR0..TIMR3.
5-203
Register Description (TIMR3)
CMDRL
to ’1’.
(hdlc modes)
PEB 20542
PEF 20542
(all modes)
(all modes)
2000-09-14