PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 84

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Since only one interrupt request output is provided, the cause of an interrupt must be
determined by the CPU by reading the interrupt status registers (GSTAR, ISR0, ISR1,
ISR2, DISR, GPIS).
Figure 40
Each interrupt indication of registers ISR0, ISR1, ISR2,
selectively unmasked by resetting the corresponding bit in the corresponding mask
registers IMR0, IMR1, IMR2,
selected serial mode.
If bit ’VIS’ in register
interrupt status registers ISR0..ISR2. Interrupts masked in registers
generate an interrupt though. A read access to the interrupt status registers clears the
bits.
A global interrupt mask bit (bit ’GIM’ in register GMODE) suppresses interrupt generation
at all. To enable the interrupt system after reset, this bit must be set to ’0’.
The Global Interrupt Status Register (GSTAR) serves as pointer to pending channel
related interrupts and general purpose port interrupts.
Data Sheet
GPIM
GPIS
Interrupt Status Registers
DIMR
DISR
CCR0L
GSTAR
GPI
is set to ’1’, masked interrupt status bits are visible in the
DIMR
DMI
and GPIM. Use of these registers depends on the
Channel A
ISA2
Channel B
IMR2 (ch A)
84
ISR2 (ch A)
ISA1
IMR1 (ch A)
ISR1 (ch A)
ISA0
IMR0 (ch A)
ISR0 (ch A)
ISB2
DISR
Functional Overview
ISB1
IMR0..IMR2
and
GPIS
ISB0
PEB 20542
PEF 20542
2000-09-14
can be
will not