PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 259

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

HDLC/SDLC/PPP
The transmission of a packet can be started by issuing an ’XF’ or ’XIF’ command via the
CMDRL
and PREAMB) are sent out optionally before transmission of the current packet starts.
If the transmit command does not include an end of message indication (CMDRL.XME),
SEROCCO-D will repeatedly request for the next data block by means of an ’XPR’
interrupt as soon as no more than 32 bytes are stored in the XFIFO, i.e. a 32-byte pool
is accessible to the CPU.
This process will be repeated until the CPU indicates the end of message per ’XME’
command, after which packet transmission is finished correctly by appending the CRC
and closing flag sequence. Consecutive packets may be transmitted as back-to-back
packets and may even share a flag (enabled via CCR1L.SFLG), if service of XFIFO is
quick enough.
In case no more data is available in the XFIFO prior to the arrival of the end-of-message
indiction (’XME’), the transmission of the packet is terminated with an abort sequence
and the CPU is notified per interrupt (ISR1.XDU, transmit data underrun). The packet
may also be aborted per software at any time (CMDRL.XRES).
The data transmission sequence, from the CPU’s point of view, is outlined in
ASYNC
The transmission of character(s) can be started by issuing a ’XF’ command via the
CMDRL
of an ’XPR’ interrupt as soon as no more than 32 bytes are stored in the XFIFO, i.e. a
32-byte pool is accessible to the CPU. Transmission may be aborted per software
(CMDRL.XRES).
BISYNC
The transmission of a block can be started by issuing an ’XF’ command via the
register. Further handling of data transmission with respect to preamble transmission
and command ’XME’ is similar to HDLC/SDLC mode. After ’XME’ command has been
issued, the block is finished by appending the internally generated CRC if enabled (refer
to description of register CCR2H).
In case no more data is available in the XFIFO prior to the arrival of ’XME’, the
transmission of the block is terminated with IDLE and the CPU is notified per interrupt
(ISR1.XDU). The block may also be aborted per software (CMDRL.XRES). The data
transmission flow, from the CPU’s point of view, is outlined in
Data Sheet
register. If enabled, a specified number of preambles (refer to registers
register. SEROCCO-D will repeatedly request for the next data block by means
259
Figure
59.
Programming
PEB 20542
PEF 20542
Figure
2000-09-14
CMDRL
CCR2H
59.