PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 178

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
RFTH(1:0)
Receive FIFO Threshold
This bit field defines the level up to which the SCC receive FIFO is filled
with valid data before an ’RPF’ interrupt is generated.
(In case of a ’frame end / block end’ condition the SEROCCO-D notifies
the CPU immediately, disregarding this threshold.)
The meaning depends on the selected protocol engine:
HDLC Modes:
RFTH(1:0)
’00’
’01’
’10’
’11’
ASYNC/BISYNC Mode:
RFTH(1:0)
’00’
’01’
’10’
’11’
Threshold level in number of data bytes.
32 byte
16 byte
4 byte
2 byte
Threshold level in number of data bytes (DB) and status
bytes (SB) depending on bit ’RFDF’:
RFDF = ’0’
1 DB
4 DB
16 DB
32 DB
5-178
Register Description (CCR3H)
RFDF = ’1’
1 DB + 1 SB
2 DB + 2 SB
8 DB + 8 SB
16 DB + 16 SB
PEB 20542
PEF 20542
(all modes)
2000-09-14