PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 85

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

3.6
3.6.1
General purpose pins are provided on pins GP0...GP2.
Every pin is separately programmable via the General Purpose Port Direction register
GPDIR
value).
If defined as output, the state of the pin is directly controlled via the General Purpose Port
Data register GPDAT. Read access to these registers delivers the current state of all
GPP pins (input and output signals).
If defined as input, the state of the pin is monitored. The signal state of the corresponding
GP pins is sampled with a rising edge of CLK and is readable via register GPDAT.
3.6.2
The GPP block generates interrupts for transitions on each input signal. All changes may
be indicated via interrupt (optional). To enable interrupt generation, the corresponding
interrupt mask bit in register
Bit GPI in the gloabl interrupt status register (GSTAR) is set to ’1’ if an interrupt was
generated by any one or more of the the general purpose port pins. The GPP pin causing
the interrupt can be located by reading the
Data Sheet
to operate as an output (bit GPnDIR=’0’) or as an input (bit GPnDIR=’1’, reset
General Purpose Port Pins
GPP Functional Description
GPP Interrupt Indication
GPIM
must be reset to ’0’.
85
GPIS
register.
Functional Overview
PEB 20542
PEF 20542
2000-09-14