PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 228

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
XPR
ALLS
XDU
XON
Transmit Pool Ready Interrupt
This bit is set to ’1’, if a transmitter reset command was executed
successfully (command bit ’XRES’ in register CMDRL) and whenever
the XFIFO is able to accept new transmit data again.
An ’XPR’ interrupt is not generated, if no sufficient transmit clock is
available (depending on the selected clock mode).
ALL Sent Interrupt
HDLC Mode:
This bit is set to ’1’:
• if the last bit of the current HDLC frame is sent out via pin TxD and no
• if an I-frame is sent out completely via pin TxD and either a valid
ASYNC/BISYNC Mode:
This bit is set to ’1’, if the last character is completely sent via pin TxD
and no further data is stored in the SCC transmit FIFO, i.e. the transmit
FIFO is empty.
Transmit Data Underrun Interrupt
This bit is set to ’1’, if the current frame was terminated by the SCC with
an abort sequence, because neither a ’frame end / block end’ indication
was detected in the FIFO (to complete the current frame) nor more data
is available in the SCC transmit FIFO.
Note: The transmitter is stopped if this condition occurs. The XDU
XON Character Detected Interrupt
This bit is set to ’1’, if the currently received character matched the XON
character programmed in register
transmitter is switched to ’XON’ state if in-band flow control is enabled
via bit ’FLON’ in register CCR2H.
further frame is stored in the SCC transmit FIFO, i.e. the transmit FIFO
is empty (Address Mode 2/1/0);
acknowledge S-frame has been received or a time-out condition
occured because no valid acknowledge S-frame has been received in
time (Automode).
condition MUST be cleared by reading register ISR1, thus bit
’XDU’ should not be masked via register IMR1.
228
XON
and indicates, that the
Register Description
(hdlc/bisync modes)
(async mode)
PEB 20542
PEF 20542
(all modes)
(all modes)
2000-09-14