PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 189

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
The following register bit fields allow flexible assignment of bit- or octet-aligned transmit
time-slots to the serial channel. For more detailed information refer to chapters
Mode 5a (Time Slot Mode)” on Page 57
on Page
TCS(2:0)
TEPCM
TTSN(6:0)
TCC(8:0)
64.
Transmit Clock Shift
This bit field determines the transmit clock shift.
Enable PCM Mask Transmit
This bit selects the additional Transmit PCM Mask (refer to register
PCMTX0..PCMTX3):
TEPCM=’0’
TEPCM=’1’
Transmit Time Slot Number
This bit field selects the start position of the timeslot in time-slot
configuration mode (clock mode 5a/5b):
Offset = 1+TTSN*8 + TCS (1..1024 clocks)
Transmit Channel Capacity
This bit field determines the transmit time-slot width in standard time-slot
configuration (bit TEPCM=’0’):
Number of bits = TCC + 1, (1..512 bits/time-slot)
Standard time-slot configuration.
The time-slot width is constant 8 bit, bit fields ’TTSN’ and
’TCS’ determine the offset of the PCM mask and ’TCC’ is
ignored. Each time-slot selected via register
PCMTX0..PCMTX3
5-189
and
“Clock Mode 5b (Octet Sync Mode)”
is an active transmit timeslot.
Register Description (TTSA3)
PEB 20542
PEF 20542
(all modes)
(all modes)
(all modes)
(all modes)
2000-09-14
“Clock