PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 154

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
HUNT
RFRD
RRES
Enter Hunt State Command
Self-clearing command bit:
HUNT=’1’
Receive FIFO Read Enable Command
Self-clearing command bit:
RFRD=’1’
Receiver Reset Command
Self-clearing command bit:
RRES=’1’
This command forces the receiver to enter its ’HUNT’
state immediately. Thus synchronization is ’lost’ and the
receiver starts searching for new SYNC characters.
This command forces insertion of a ’block end’ condition
into the RFIFO before the receive FIFO threshold is
exceeded or a block end condition (termination character
detected or time-out) is fulfilled. The execution of this
command is reported with a TCD interrupt.
The SCC receive FIFO is cleared and the receiver
protocol engines are reset to their initial state.
The SCC receive FIFO accepts new receive data from the
protocol engine immediately after receiver reset
procedure.
It is recommended to disable data reception before
issuing a receiver reset command by setting bit
CCR3L.RAC = ’0’ and enabling data reception afterwards.
A ’receiver reset’ command is recommended after all
changes in protocol mode configurations (switching
between the protocol engines HDLC/ASYNC/BISYNC or
sub-modes of HDLC).
5-154
Register Description (CMDRH)
(async/bisync modes)
(bisync mode)
PEB 20542
PEF 20542
(all modes)
2000-09-14