PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 168

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
NPRE(1:0)
ITF
OIN
Number of Preamble Repetitions
This bit field determines the number of preambles transmitted:
NPRE = ’00’ 1 preamble.
NPRE = ’01’ 2 preambles.
NPRE = ’10’ 4 preambles.
NPRE = ’11’ 8 preambles.
Interframe Time Fill
This bit selects the idle state of the transmit pin TxD:
ITF=’0’
ITF=’1’
Note: It is recommended to clear bit ’ITF’ in bus configuration modes, i.e.
One Insertion
In HDLC mode a one-insertion mechanism similar to the zero-insertion
can be activated:
OIN=’0’
OIN=’1’
continuous ’1’s are sent as idle sequence and data encoding is
NRZ.
Continuous logical ’1’ is sent during idle phase.
HDLC Mode:
Continuous flag sequences are sent (’01111110’ flag
pattern).
BISYNC Mode:
Continuous SYN characters are output.
The ’1’ insertion mechanism is disabled.
In transmit direction a logical ’1’ is inserted to the serial
data stream after 7 consecutive zeros.
In receive direction a ’1’ is deleted from the receive data
stream after receiving 7 consecutive zeros.
This enables clock information to be recovered from the
receive data stream by means of a DPLL, even in the case
of NRZ data encoding, because a transition at bit cell
boundary occurs at least every 7 bits.
5-168
Register Description (CCR2H)
(hdlc/bisync mode)
(hdlc/bisync mode)
PEB 20542
PEF 20542
(hdlc mode)
2000-09-14