TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 115

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

(3) Serial clock generator
(4) Receive counter
(5) Receive controller
operations.
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clocked by SIOCLK. The receiver uses 16 clocks for each received bit, and oversamples
each bit three times around their center (with 7th to 9th clocks). The value of a bit is
determined by voting logic which takes the value of the majority of three samples. For
example, if the three samples of a bit are 1, 0 and 1, then that bit is interpreted as a 1;
if the three samples of a bit are 0, 0 and 1, then that bit is interpreted as a 0.
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This block generates a basic clock (SIOCLK) for controlling transmit and receive
The receive counter is a 4-bit binary up counter used in UART mode. This counter is
I/O interface mode
UART mode
I/O interface mode
UART mode
to 0, the output clock from the baud rate generator is divided by two to generate
the SIOCLK clock.
1, the external SCLK clock is used as the SIOCLK clock; the SC0CR<SCLKS> bit
determines the active clock edge.
the system clock (f
external SCLK0 clock according to the setting of the SC0MOD0<SC1:0> field.
to 0, the receive controller samples the RXD0 input at the rising or falling edge of
the shift clock driven out from the SCLK pin.
1, the receive controller samples the RXD0 pin at either the rising or falling edge of
the SCLK clock, as programmed in the SC0CR<SCLKS> bit.
is detected (at least two 0s are detected among three samples), the receive
controller begins sampling the incoming data streams. The start bit, each data bit
and the stop bit are sampled three times for 2-of-3 majority voting.
When the SCLK pin is configured as an output by clearing the SC0CR<IOC> bit
When the SCLK pin is configured as an input by setting the SC0CR<IOC> bit to
The SIOCLK clock is selected from a clock produced by the baud rate generator,
When the SCLK pin is configured as an output by clearing the SC0CR<IOC> bit
When the SCLK pin is configured as an input by setting the SC0CR<IOC> bit to
The receive controller contains the start bit detection logic. Once a valid start bit
SYS
), the trigger output signal from the timer TMRA0, and the
91CW40-113
TMP91CW40
2008-09-19