TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 29

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

3.4
Interrupts
on-chip interrupt controller.
register <IFF2:0>. If the sent priority level is higher than or equal to the interrupt mask level,
the CPU accepts the interrupt. The contents of the <IFF2:0> bits can be modified using the EI
instruction in the format of EI num, where num is the value to be set in <IFF2:0>. For example,
“EI 3” causes the CPU to accept maskable interrupts having a priority level of 3 or higher, as
specified with the interrupt controller, as well as all nonmaskable interrupts. The DI
instruction, which sets <IFF2:0> to 7, has the same effect as “EI 7”. It is used to prevent the
CPU from accepting maskable interrupts because maskable interrupts can have priority levels
of only up to 6. The EI instruction takes effect immediately after it is executed.
micro DMA mode, where the CPU automatically transfers data (1 byte, 2 bytes or 4 bytes). This
mode enables faster data transfer to internal/external memory and internal I/O.
with the soft start feature.
is assigned one of six priority levels (variable) while nonmaskable interrupts have the highest
priority level of 7 (fixed).
source to the CPU. If two or more interrupts occur simultaneously, it sends the highest of their
priority levels (7 if a nonmaskable interrupt occurs) to the CPU.
Interrupt processing is controlled by the CPU interrupt mask register SR <IFF2:0> and the
The TMP91CW40 supports the following 43 interrupt sources:
Each interrupt source has a unique interrupt vector number (fixed). Each maskable interrupt
When an interrupt occurs, the interrupt controller sends the priority level of that interrupt
The CPU compares the sent priority level with the contents of the CPU interrupt mask
In addition to general interrupt servicing, as described above, the TMP91CW40 supports
A micro DMA request can be issued either using an interrupt source or programmatically
Figure 3.4.1 shows the overall flow of interrupt servicing.
•
•
•
9 CPU internal interrupts
7 external interrupt pins (
27 internal I/O interrupts
(Software interrupts and interrupts triggered when an undefined instruction is
executed)
91CW40-27
NMI
, INT0, INT1, KWI0 to KWI3)
TMP91CW40
2008-09-19