TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 131

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

1. Put all the master and salve controllers in 9-bit UART mode.
2. Enable the receiver in each slave controller by setting the SC0MOD0 <WU> bit to 1.
3. The master controller transmits an address character (i.e., select code) that identifies a
4.
5.
6. Slave controllers not addressed (with <WU> = 1) continue to monitor the data stream,
Protocol
slave controller. The address character has the most-significant bit (bit 8) set to 1.
but discard any characters with the most-significant bit (RB8) cleared, and thus does
not generate receive-done interrupts (INTRX). The addressed slave controller (with
<WU> = 0) can transmit data to the master controller to notify that it has successfully
received the message.
Each slave controller compares the received select code to its own select code and clears
the <WU> bit if they match.
The master controller transmits data character to the selected slave controller (with
the SC1MOD0<WU> bit cleared). Data characters have the most-significant bit (bit 8)
cleared to 0.
Start
Start
Bit0
Bit0
1
1
Slave controller select code
2
91CW40-129
2
3
3
Data
4
4
5
5
6
6
7
7
“1”
8
Bit8
“0”
Stop
Stop
TMP91CW40
2008-09-19