TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 22

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

3.3.6
CPU
I/O ports
TC1 to TC3, TC5 to TC8
SIO0 to SIO3
AD converter
WDT
RTC, MLD
LCDD
Interrupt controller
Standby Control
(1) HALT mode
SYSCR2<HALTM1:0>
modes–IDLE2, IDLE1 or STOP–as specified by the SYSCR2 <HALTM1:0> bits.
HALT mode
Executing the HALT instruction causes the TMP91CW40 to enter one of the HALT
The characteristics of IDLE2, IDLE1 and STOP modes are as follows:
Table 3.3.3 shows the operation of each circuit block in HALT modes.
a. IDLE2: The CPU stops.
b. IDLE1: Only the oscillator, RTC(real-time clock) and MLD are operational.
c. STOP: The whole TMP91CW40 stops.
Table 3.3.3 TMP91CW40 Circuit Blocks in HALT Modes
SIO0
SIO1
SIO2
SIO3
AD converter
WDT
Table 3.3.2 IDLE2 Mode Register Settings
Each internal I/O can be selectively enabled and disabled through use of
a register bit in an SFR, as shown in Table 3.3.2.
Internal I/O
Selectable programmatically on
a block-by-block basis
Holding the states when the HALT instruction was
91CW40-20
IDLE2
ON
ON
11
SC0MOD1<I2S0>
SC1MOD1<I2S1>
SC2MOD1<I2S2>
SC3MOD1<I2S3>
ADMOD1<I2AD>
WDMOD<I2WDT>
executed
ON
SFR
OFF
IDLE1
10
OFF
See Table 3.3.6
STOP
01
TMP91CW40
2008-09-19